1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a write circuit for use with a dynamic random-access memory (DRAM).
2. Description of the Related Art
One circuit arrangement for selecting write switches for a conventional semiconductor memory device will be described below. FIG. 1 of the accompanying drawings shows the layout of a circuit arrangement for selecting write switches of a DRAM which has a plurality of memory cell arrays and a plurality of sense amplifier columns. As shown in FIG. 1, sense amplifier columns 21, 22, 23 are disposed in sandwiching relationship to memory cells 31, 32. Write switch signal output circuits WSS21, WSS24 are disposed respectively at the opposite ends along word lines of the sense amplifier column 21. Similarly, write switch signal output circuits WSS22, WSS25 are disposed respectively at the opposite ends along word lines of the sense amplifier column 22, and write switch signal output circuits WSS23, WSS26 are disposed respectively at the opposite ends along word lines of the sense amplifier column 23. Write data output circuits WBUF21, WBUF22, WBUF23 are disposed at one of the opposite ends along word lines of the sense amplifier columns 21, 22, 23, respectively.
The sense amplifier columns 21, 22, 23 have respective pairs of write data signal lines WIT21/WIN21, WIT22/WIN22, WIT23/WIN23, parallel to word lines, for outputting complementary write data signals. Digit lines extend parallel to write enable signal lines which output a write enable signal (a write timing control signal) WE for controlling write timing.
The write data output circuits WBUF21, WBUF22, WBUF23 output complementary write data signals respectively to the paired write data signal lines WIT21/WIN21, WIT22/WIN22, WIT23/WIN23, and also output write select signals WSEL21, WSEL22, WSEL23 respectively to the write switch signal output circuits WSS21, WSS24, the write switch signal output circuits WSS22, WSS25, and the write switch signal output circuits WSS23, WSS26.
The write switch signal output circuits WSS21, WSS24, the write switch signal output circuits WSS22, WSS25, and the write switch signal output circuits WSS23, WSS26 are supplied with a write enable signal WE and respective write select signals WSEL21, WSEL22, WSEL23, and generate and output write switch signals WSW21, WSW24, write switch signals WSW22, WSW25, and write switch signals WSW23, WSW26, respectively, for controlling the turning-on/off of transfer gates which interconnect the digit lines and the write data signal lines. The write switch signals are applied to control terminals (gate electrodes) of the transfer gates, which control the connection and disconnection of digit lines and write data signal lines that are selected by column selection signals.
As shown in FIG. 1, one write data output circuit and two write switch signal output circuits are associated with each sense amplifier column because write switch signals impose a greater load than write data signals. Two write switch signal output circuits provided per sense amplifier column reduce the load imposed by write switch signals to half, improving characteristics in a write mode of operation of the DRAM.
FIG. 2 of the accompanying drawings shows a circuit arrangement of each of the write switch signal output circuits WSS21.about.WSS26. As shown in FIG. 2, the write switch signal output circuits WSS21.about.WSS26 are supplied with write select signals WSEL21, WSEL22, WSEL23 from the respective write data output circuits WBUF21, WBUF22, WBUF23 and output respective write switch signals WSW21.about.WSW26. The write switch signal output circuits WSS21.about.WSS26 are arranged such that the write switch signals WSW21.about.WSW26 outputted thereby go high when the write select signals WSEL21, WSEL22, WSEL23 go high and also the write timing control signal WE goes high. Specifically, each of the write switch signal output circuits WSS21.about.WSS26 is of an ANDing structure comprising an NAND gate NAND and an inverter INV. When the write data output circuits WBUF21, WBUF22, WBUF23 are activated, they output write data signals WIT21/WIN21, WIT22/WIN22, WIT23/WIN23, and the write select signals WSEL21.about.WSEL23 outputted thereby go high. The write switch signals WSW21.about.WSW26 may be turned on for only those sense amplifier columns to which write data are outputted. Therefore, the write switch signals WSW21.about.WSW26 are properly selected by making the write select signals WSEL21, WSEL22, WSEL23 high only when the write data output circuits WBUF21, WBUF22, WBUF23 are activated.
The conventional semiconductor memory device in which write switch signal output circuits are selected by write select signals, particularly, the circuit arrangement as shown in FIG. 1, is disadvantageous in that the chip size thereof is relatively large because signal lines for the write select signals run through the sense amplifier columns.